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Data Sh eet, V 1.0D3, Mar. 2001
82C900
Standalone TwinCAN Controller
M i c r o c o n t ro l le r s
Never
stop
thinking.
Edition 2001-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sh eet, V 1.0D3, Mar. 2001
82C900
Standalone TwinCAN Controller
M i c r o c o n t ro l le r s
Never
stop
thinking.
82C900 Preliminary Revision History: Previous Version: Page
2001-03 -
V 1.0D3
Subjects (major changes since last revision)
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Preliminary
Standalone TwinCAN Controller
82C900
82C900
Architectural Overview The Standalone TwinCAN device provides several submodules to control the data flow and to configure the peripheral function: Features: * Two interface channels are implemented for the communication with a host device: - the Multiplexed Data/Address Bus can be used by an external CPU to read and write the TwinCAN's internal registers for initial configuration and control during normal operation. The standard Infineon Bus Mode and the Motorola Bus Mode can be handled. - alternatively, a Synchronous Serial Channel (SSC) may be selected to read out the initial TwinCAN's register configuration from a serial EEPROM. The SSC can be also used by an external control device (microcontroller, CPU, etc.) in order to exchange control and status information. * Both communication channels are based on byte transfers. In order to minimize the communication overhead, all internal 16 bit and 32 bit wide registers can be accessed in Page Mode requiring only one address byte. * Powerful initialization mechanism for all registers, the device can be configured via EEPROM, based on CAN messages or by an external host device. * Additional input/output functionality controlled by CAN messages. The transmission of CAN messages can be triggered by input pins if the SSC is used for communication. * The clock control unit can be supplied with an external clock. Alternatively, an on-chip oscillator may be used to generate a clock driving also an external device via an output pin. * Power Saving features have been implemented. A Sleep Mode and a Power-Down Mode can be activated in order to minimize the power consumption. The clock control of the device can be controlled by CAN messages. * The internal power saving status can be monitored at output pins. This allows flexible and powerful system partitioning. * The Device Controller unit generates the internal target address by concatenating the contents of the PAGE register with the address delivered by the appropriate host read/ write access. * The Interrupt Control unit passes the interrupt requests generated by the TwinCAN controller to the external host via selectable output pins. * The Port Control unit can be used to select the required functionality of the port pins operating as communication channel, CAN node function monitor, interrupt request line or general purpose I/O. Furthermore, the slew rate of pins configured for output operation can be adjusted via this module.
Data Sheet 5 V 1.0D3, 2001-03
82C900
Preliminary The TwinCAN module permits the connection and autonomous handling of two independent CAN buses. * Full-CAN module with 32 message objects, which can be independently assigned to one of the two buses. * The CAN protocol version 2.0B active with standard and extended identifiers can be handled. * The full CAN baud rate range is supported. * Scalable FIFO mechanism for reception and transmission in order to improve the realtime behavior of the system. * Built-in automatic gateway functionality for data exchange between both CAN buses. The gateway feature can also be used for automatic reply to received messages (lifesign: "I got it!"). * Powerful interrupt structure, permitting application-specific interrupt generation. * Remote frames can be monitored. * Enhanced acceptance filtering (an acceptance mask for each message object). * A 16 bit frame count / timestamp is implemented for each message object. * Analyzing mode (no dominant level will be sent) supported. Figure 1 shows a block diagram of the 82C900 device architecture.
4
CTRL0..CTRL3
8
Port Control Interrupt Control Clock control SSC
CAN data
P0..P7
2 int
MODE0, MODE1
2
OUT0, OUT1
clk 2
CAN CAN Node Node A B
XTAL1, XTAL2
2
addr
RESET, RDY
2
data
Message Object Buffer
RXDCA, RXDCB
2
TXDCA, TXDCB
Device Control
TwinCAN Control
Figure 1
Standalone TwinCAN Architecture
Note: The CAN bus transceivers are not integrated and have to be connected externally.
Data Sheet
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82C900
Preliminary Application Fields The Standalone TwinCAN device 82C900 can be used in application requiring one or two independent CAN nodes. The built-in FIFO and gateway features minimize the CPU load for the message handling and lead to an improved real-time behavior. The access to the internal registers can be handled via a parallel or a serial interface, adapted to a large variety of applications. The interface selection is done via the two MODE pins, which can be directly connected to the supply voltage or via pull-up/down resistors (of about 10-47 kOhm). In all modes, the clock generation can be controlled either by the 82C900 device or by the system it is connected to. Connection to a Host Device via the Parallel Interface The 82C900 can be connected to a host device via a parallel 8 bit multiplexed interface. Therefore, pin MODE0 has to be 0, whereas pin MODE1 selects, whether an Infineon(Intel-) compatible or an Motorola-compatible protocol is handled. In this mode, the device can be easily used to extend the CAN capability of a system. The internal registers can be accessed in pages of 256 bytes per page. An additional RDY output indicates when the device is ready to be accessed. This signal can be used to detect an overload situation of the CAN device (too many host accesses to the TwinCAN module). One interrupt output line (OUT1) is always available, a second one (OUT0) can be used as clockout pin or as another interrupt output.
CAN Bus A Transceiver
RXDCA, TXDCA
CAN Bus B Transceiver
RXDCB, TXDCB
82C900 TwinCAN Module Parallel Interface
AD7..0 CTRL3..0 RDY
Clock Control Interrupt Control
OUTx
Host
Figure 2
Data Sheet
Host Connection via the Parallel Interface
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82C900
Preliminary Connection to a Host Device via the Serial Interface The second possibility to connect the 82C900 to a host device is via the serial interface. This mode is selected if the pin MODE0=1 and MODE1=0. The standard four-line SPI-compatible interface has been extended by a RDY signal, which indicates that the serial interface is ready for the next access by the host. The page size is reduced to 128 bytes per page, because the MSB of the address byte contains a read/write indication. A special incremental access mode has been implemented in order to reduce significantly the number of transferred bytes for consecutive register accesses. The 8 remaining I/O pins from the unused parallel interface are controlled by a port control logic and can be used as I/O extension. These lines can be read or written by the serial channel or by CAN messages. Furthermore, these lines can be programmed as additional interrupt output lines in order to increase the number of independent interrupts. The output lines OUT0 and OUT1 have the same functionality in the case a parallel interface or a serial interface connects the 82C900 to a host device.
CAN Bus A Transceiver
RXDCA, TXDCA
CAN Bus B Transceiver
RXDCB, TXDCB
82C900 TwinCAN Module Port Control
I/O7..0
Clock Control Interrupt Control
OUTx
Serial Interface
CTRL3..0 RDY
Input/Output Extension
Figure 3
Host
Host Connection via the Serial Interface
Data Sheet
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82C900
Preliminary Operation without Host Device The standalone functionality comprises an additional mode, leading to a low-cost system, which does not require any external host device. This mode can be selected by setting the input pins MODE0 and MODE1 to 1. The best solution are pull-up resistors (about 10 to 47 kOhm). After the reset phase, the MODE pins can be enabled to control the power-down functionality of the entire connected system by indicating the internal status of two clock control bits. The power-down functionality can run completely via CAN messages (sleep and wake-up by CAN messages). The initialization sequence is automatically started from an external non-volatile memory, a serial (SPI-compatible) EEPROM. The data, which is read out from the EEPROM permits the user to initialize the registers with the desired values in a freely programmable order. Changes in the application only lead to modified data stored in the non-volatile memory. For example, the bit timing, one message object and some control registers are set up via the data read from the EEPROM. Then, the initialization can continue via CAN messages. The 8 remaining I/O pins from the unused parallel interface are controlled by a port control logic and can be used as I/O extension. These lines can be read or written by CAN messages.
CAN Bus A Transceiver
RXDCA, TXDCA
CAN Bus B Transceiver
RXDCB, TXDCB
82C900 TwinCAN Module Port Control
I/O7..0
Clock Control Device Control
Serial Interface
CTRL3..0
Input/Output extension
Figure 4
Serial EEPROM
Power-Down Indication
Connection to a Serial EEPROM
Data Sheet
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82C900
Preliminary Pin Configuration
RXDCA TXDCA RESET XTAL1 XTAL2 OUT0 VDD VSS CTRL0 CTRL2 P0 P2 P4 P6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RXDCB TXDCB MODE0 MODE1 RDY OUT1 VDD VSS CTRL1 CTRL3 P1 P3 P5 P7
Figure 5
82C900 Pin Configuration
Pin Definition Table 1 Symbol RXDCA Pin Definitions and Functions Pin I/O 1) Function Number 1 I Receiver Input of CAN Node A Receiver input of CAN node A, connected to the associated CAN bus via a transceiver device. Transmitter Output of CAN Node A TXDCA delivers the output signal of CAN node A. The signal level has to be adapted to the physical layer of the CAN bus via a transceiver device. Receiver Input of CAN Node B Receiver input of CAN node B, connected to the associated CAN bus via a transceiver device.
TXDCA
2
O
RXDCB
28
I
Data Sheet
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82C900
Preliminary Table 1 Symbol TXDCB Pin Definitions and Functions (cont'd) Pin I/O 1) Function Number 27 O Transmitter Output of CAN Node B TXDCB delivers the output signal of CAN node B. The signal level has to be adapted to the physical layer of the CAN bus via a transceiver device. Reset A low level on this pin resets the device. Ready Signal Output signal indicating that the standalone device is ready for data transfer. Control 0 MODE0=0: Chip Select CS Input used as Chip Select for the device. MODE0=1: Select Slave SLS MODE1=0: Input used to enable SSC action when active. MODE1=1: Output used to select a slave when active. Control 1 MODE0=0: Address Latch Enable or Address Strobe, ALE or AS Input used for latching the address from the multiplexed address/data bus. MODE0=1: Serial Channel Clock SCLK Input/output of the SSC clock. MODE1=0: Clock input MODE1=1: Clock output CTRL2 10 I/O Control 2 MODE0=0: MODE1=0: MODE1=1: MODE1=1: MODE0=1: MODE1=0: MODE1=1: Write or Read/Write, WR or R/W Input used as write signal WR R/W=0: Data transfer direction = write R/W=1: Data transfer direction = read Master Transmit Slave Receive MTSR Serial data input Serial data output
RESET RDY
3 24
I O
CTRL0
9
I/O
CTRL1
20
I/O
Data Sheet
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82C900
Preliminary Table 1 Symbol CTRL3 Pin Definitions and Functions (cont'd) Pin I/O 1) Function Number 19 I/O Control 3 MODE0=0: MODE1=0: MODE1=0: MODE0=1: MODE1=0: MODE1=1: Read or Read/Write Enable, RD or E Input used as read signal RD Read/write enable Master Receive Slave Transmit MRST Serial data output Serial data input
P7 P6 P5 P4 P3 P2 P1 P0 OUT0 2)
15 14 16 13 17 12 18 11 6
I/O
Parallel Bus MODE0=0: 8-bit Address/ Data Bus AD[7:0] Address and data bus AD7..AD0 in 8-bit multiplexed modes. MODE0=1: 8-bit parallel I/O Port IO[7:0] Programmable 8-bit general purpose I/O-port IO7..IO0.
O
Output Line 0 The logic 0 level at this pin indicates an interrupt request to the external host device if selected as interrupt output. The interrupt line will be active if there is a new pending interrupt request for interrupt node 0 (according to register GLOBCTR). If selected as clock output, the functionality is defined by register CLKCTR.
OUT1
23
O, Output Line 1 open The logic 0 level at this pin indicates an interrupt request drain to the external host device. The interrupt line will be active if there is a new pending interrupt request for interrupt node 1 (according to register GLOBCTR). I/O, Interface Selection open Pin MODE0 selects whether the on-chip SSC or an 8-bit drain multiplexed bus are used to access the TwinCAN device. MODE0=0: 8-bit multiplexed address/data bus MODE0=1: on-chip SSC After registering the initial state of MODE0 with the rising edge of the reset signal, the respective pin can be used as additional general purpose or special function I/O line according register IOMODE4.
12 V 1.0D3, 2001-03
MODE0 3)
26
Data Sheet
82C900
Preliminary Table 1 Symbol MODE1 Pin Definitions and Functions (cont'd) Pin I/O 1) Function Number 25 I/O, Interface Mode Selection open Pin MODE1 determines the access mode of the host drain device. MODE0=0: 8-bit multiplexed bus MODE1=0: Infineon / Intel mode, (RD, WR) MODE1=1: Motorola mode, (R/W, E) MODE0=1: On-chip SSC MODE1=0: SSC is slave, host device is master MODE1=1: SSC is master, external serial EEPROM is slave After registering the initial state of MODE1 with the rising edge of the reset signal, the respective pin can be used as additional general purpose or special function I/O line according register IOMODE4. I XTAL1 Input of the inverting oscillator amplifier and input to the internal clock generation circuit. When the 82C900 device is provided with an external clock, XTAL1 should be driven while XTAL2 is left unconnected. Minimum and maximum high and low pulse width as well as rise/fall times specified in the AC characteristics must be respected. XTAL2 Output of the inverting oscillator amplifier. Ground, both pins must be connected. Power Supply, both pins must be connected.
XTAL1
4
XTAL2 VSS VDD
1)
5 21, 8 22, 7
O 0V +5V
The slew rate of the output pins OUT0, OUT1, CTRL1..3, P0..P7, TXDCA and TXDCB can be defined by the bit fields SLR0..3 in register GLOBCTR. After reset, this pin is configured as clock output, see register CLKCTR. The initial logic state on pins MODE0 and MODE1 is registered with the rising edge of the RESET input. Afterwards, both pins can be used as additional I/O lines, according to functionality specified in register IOMODE4.
2) 3)
Data Sheet
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82C900
Preliminary Register Address Map All Shell and Kernel registers, implemented for controlling the 82C900 device, are summarized in Table 0-1; detailed information about each register is provided in the respective module description chapter. Note: Accesses to addresses which are not specified as registers in the following register address map are forbidden. Table 0-1 Summary of Registers Register Symbol GLOBCTR INTCTR CLKCTR IOMODE0 IOMODE2 IOMODE4 INREG OUTREG CANPWD CANIO CANINIT PAGE CAB INITCTR RXIPND TXIPND ACR ASR AIR ABTR
14
Register Name Standalone Shell Registers Global Device Control Register Interrupt Control Register CAN Clock Control Register Input/Output Mode Register 0 Input/Output Mode Register 2 Input/Output Mode Register 4 Input Value Register (8-bit port) Output Value Register (8-bit port) CAN Power-Down Control Register CAN Input/Output Control Register CAN Initialization Control Register Paging Mode Register (accessible in all pages) CAN RAM Address Buffer Register Initialization Control Register TwinCAN Kernel, Common Registers CAN Receive Interrupt Pending Register CAN Transmit Interrupt Pending Register TwinCAN Kernel, Node A Registers CAN Node A Control Register CAN Node A Status Register CAN Node A Interrupt Pending Register CAN Node A Bit Timing Register
Data Sheet
Address
Reset Value
1)
0010H 0012H 0014H 0020H 0022H 0024H 0026H 0028H 0040H 0042H 0044H XX7CH 007EH 02F0H 0284H 0288H 0200H 0204H 0208H 020CH
A0 00H 00 00H 00 24H 00 00H 00 00H 00 00H 00 00H 00 00H 00 00H 00 00H 00 00H 00 00H 00 00H 0103 0000H 0000 0000H 0000 0000H 0000 0001H 0000 0000H 0000 0000H 0000 0000H
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82C900
Preliminary Table 0-1 Summary of Registers (cont'd) Register Symbol AFCR AIMR0 AIMR4 AECNT BCR BSR BIR BBTR BFCR BIMR0 BIMR4 BECNT MSGDRn0 MSGDRn4 Address 0210H 0214H 0218H 021CH 0220H 0240H 0244H 0248H 024CH 0250H 0254H 0258H 025CH 0260H 0300H + n*20H 0304H + n*20H 0308H + n*20H 030CH + n*20H 0310H + n*20H 0314H + n*20H 0318H + n*20H Reset Value
1)
Register Name
CAN Node A Global Int. Node Pointer Reg. AGINP CAN Node A Frame Counter Register CAN Node A INTID Mask Register 0 CAN Node A INTID Mask Register 4 CAN Node A Error Counter Register TwinCAN Kernel, Node B Registers CAN Node B Control Register CAN Node B Status Register CAN Node B Interrupt Pending Register CAN Node B Bit Timing Register CAN Node B Frame Counter Register CAN Node B INTID Mask Register 0 CAN Node B INTID Mask Register 4 CAN Node B Error Counter Register CAN Message Object n Data Register 0 CAN Message Object n Data Register 4
0000 0000H 0000 0000H 0000 0000H 0000 0000H 0060 0000H 0000 0001H 0000 0000H 0000 0000H 0000 0000H 0000 0000H 0000 0000H 0000 0000H 0000 0000H 0060 0000H 0000 0000H 0000 0000H 0000 0000H FFFF FFFFH 0000 5555H 0000 0000H 0000 0000H
CAN Node B Global Int. Node Pointer Reg. BGINP
TwinCAN Kernel, Message Object Registers
CAN Message Object n Arbitration Register MSGARn CAN Message Object n Acceptance Mask Register CAN Message Object n Message Control Register CAN Message Object n Message Configuration Register CAN Message Object n Gateway / FIFO Control Register
1)
MSGAMRn MSGCTRn MSGCFGn MSGFGCRn
Registers with 32-bit reset values are located in the CAN RAM and have to be accessed accordingly. The other registers are standard SFRs, which have 16-bit reset values.
Data Sheet
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82C900
Preliminary Absolute Maximum Ratings Table 2 Parameter Storage temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation Absolute Maximum Rating Parameters Symbol Limit Values min. max. 150 6.5 C V V mA mA Unit Notes
TST VDD VIN
-65 -0.5 -0.5 -10
VDD+0.5
10 |100|
PDISS
480
mW
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN>VDD or VINData Sheet
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82C900
Preliminary Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the device. All parameters, specified in the following sections, refer to the normal operating conditions, unless otherwise noticed. The timings refer to the fast edge mode. Table 3 Parameter Standard digital supply voltage Digital ground voltage Overload current Absolute sum of overload currents External Load Capacitance Ambient temperature
1)
Operating Condition Parameters Symbol Limit Values min. max. 5.5 5.5 5 50 |100| 125 V V V mA mA pF C SAK 82C900 Active mode, Unit Notes
VDD
4.5 2.5 1)
fmax = 25 MHz
Power-Down mode Reference voltage Per pin 2)
4) 3)
VSS IOV
|IOV|
CL
0 -40
TA
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode. The clock frequency has to be reduced to operate with a voltage supply below 4.5V. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < VSS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Not 100% tested, guaranteed by design characterization Not 100% tested, guaranteed by design characterization.
2)
3) 4)
Data Sheet
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82C900
Preliminary DC Characteristics Operating Conditions apply. Table 4 Parameter Input low voltage (XTAL1) Input high voltage (XTAL1) Input low voltage (other pins) Input high voltage (other pins) Output low voltage 1) (P0..P7) Output high voltage (P0..P7) Output low voltage (other pins) Output high voltage 2) (other pins) Input leakage current RESET inactive current RESET active current XTAL1 input current Pin capacitance 6) (digital inputs/outputs)
1) 2)
DC Characteristics under Normal Operation Conditions Symbol Limit Values min. max. 0.3 VDD V V - - - - Unit Test Condition
VIL VIH VIL VIH VOLP VOHP VOL VOH IOZ IRSTH 4) IRSTL 5) IIL CIO
- 0.5
0.7 VDD VDD + 0.5 - 0.5
0.2 VDD V - 0.1 V V V V V V V nA A A A pF
0.2 VDD VDD + 0.5 + 0.9 - 2.4 - 2.4 - - -100 - - 0.45 - 0.45 - 500 -10 - 20 10
IOLP = 5 mA IOHP = -5 mA IOHP = -0.5 mA IOL = 2.4 mA IOH = -2.4 mA IOH = -0.5 mA 0.45V < VIN < VDD VIN = VIH VIN = VIL 0 V < VIN < VDD f = 1 MHz TA = 25 C
1)
0.9 VDD -
0.9 VDD -
3)
The sum of | IOHP |, IOLP must not exceed 20mA. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. These parameters describe the RESET pull-up, which equals a resistance of ca. 50 to 250 K. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. Not 100% tested, guaranteed by design characterization.
3) 4) 5) 6)
Data Sheet
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82C900
Preliminary Power Consumption Operating Conditions apply. Table 5 Parameter Power supply current (5V active) with all elements active Power Consumption Symbol Limit Values min. max. 80 1.5 10 mA mA A RESET = VIH fCAN = 25 MHz 1) RESET = VIH fCAN = 25 MHz RESET = VIH Unit Test Condition
IDD5
2)
- - -
Sleep mode supply current (5V) IIDX5 (oscillator running, clock gated off) Power-down mode supply current (5V) (oscillator stopped)
1)
IIDO5
The supply current is a function of the operating frequency. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. The oscillator also contributes to the total supply current. The given values refer to the worst case. For lower oscillator frequencies the respective supply current can be reduced accordingly. This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
2)
Data Sheet
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82C900
Preliminary AC Characteristics Operating Conditions apply. Table 6 Parameter Oscillator period High time Low time
1)
External Clock Drive XTAL1 Symbol
1)
Direct Drive (1:1) min. max. - - - 40 10 15
Unit ns ns ns
TCAN
The clock input signal must reach the defined levels VIL and VIH.
Assuming a maximum access rate from an external host to the CAN RAM via the communication interface (worst case, parallel interface), the CAN protocol can still be handled on both nodes with 1 Mbps if the clock frequency fCAN is 24 MHz. For additional data handling features (FIFO, gateway, etc.), a higher frequency should be used, the access rate to the device has to be reduced or a lower baud rate has to be selected. Under worst case access conditions and CAN traffic, a baud rate of 500 kbps for each node can be achieved with full data handling functionality with fCAN=24 MHz. CAN input delay, output delay: typ. 15 ns
Data Sheet
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82C900
Preliminary 8-Bit Multiplexed Bus Infineon/ Intel Compatibility Mode The bus access is internally fully synchronized, asynchronous accesses are supported.
Read Timing
t LHLL
ALE
t RLLH
t AVLL t LLAX
AD7-0 A7-0 data out
t LLRL
RD
t RLDV
t RHDZ
t LLCL t RLRH
CS
Write Timing
t LHLL
ALE
t AVLL t LLAX
AD7-0 A7-0 data in
t LLWL
WR
t WLDS
t WHDZ t WHLH
t LLCL t WLWH
t WHCH
CS
Figure 6
Timing of Multiplexed Address/Data bus with MODE1 = 0
Data Sheet
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82C900
Preliminary Operating Conditions apply. Parameter Address valid to ALE low Address hold after ALE low ALE high time ALE low to RD low ALE low to WR low ALE low to CS low Data setup to WR high Input data hold after WR high WR pulse width WR high to next ALE high (if the next access targets the device) WR high to next ALE high (if the next access doesn't target the device) WR high to CS high RD pulse width (short read) RD pulse width (long read) RD low to data valid (short read) RD low to data valid (long read) RD low to next ALE high (short read) RD low to next ALE high (long read) Data float after RD high Symbol
t AVLL t LLAX t LHLL t LLRL t LLWL t LLCL t WLDS t WHDZ t WLWH t WHLH t WHLH
Limit Values min. 5 10 10 10 10 10 10 10 1.5 TCAN 10 TCAN 4 TCAN +15 max. - - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns ns
t WHCH t RLRH t RLRH t RLDV t RLDV t RLLH t RLLH t RHDZ
0 1.5 TCAN 8 TCAN + 25 - - 8 TCAN 25 -
- - - 25 25 + 8 TCAN - - 25
ns ns ns ns ns ns ns ns
Data Sheet
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82C900
Preliminary 8-Bit Multiplexed Bus Motorola Compatibility Mode The bus access is internally fully synchronized, asynchronous accesses are supported.
Read Timing AD7-0
t EHSH
A7-0 data out
t AVSL t SLAX
AS
t SHSL
E
t SLEH
t EHDW
t ELDZ
R/W
t RSEH t CLSL
t EHEL
t ELCH
CS
Write Timing
AD7-0
A7-0
data in
t AVSL t SLAX
AS
t ELDS
t ELDH t ELSH
t SHSL
E
t SLEH
t RSEH
R/W
t EHEL
t ELCH
t CLSL
CS
Figure 7
Timing of Multiplexed Address/Data bus with MODE1 = 1
Data Sheet
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82C900
Preliminary Operating Conditions apply. Parameter Address valid to AS low Address hold after AS low Data float after E low E high to data valid output Input data setup to E low Input data hold after E low E high time AS high time Setup time of R/W to E high AS low to E high CS low to E high E low to CS high E low to next AS high (for write) (if the next access targets the device) E low to next AS high (for write) (if the next access doesn't target the device) E high to next AS high (for read) Symbol
t AVSL t SLAX t ELDZ t EHDV t ELDS t ELDH t EHEL t SHSL t RSEH t SLEH t CLSL t ELCH t ELSH t ELSH
Limit Values min. 5 10 - - 10 10 1.5 TCAN 10 0 10 0 0 10 TCAN 4 TCAN + 15 max. - - 25 25 - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t EHSH
8 TCAN
-
ns
Data Sheet
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82C900
Preliminary Timings of the SSC In the case that the SSC is used in slave mode without the RDY signal, the following timings have to be respected: Parameter Min. Time (access to TwinCAN registers) 1100 4 2 2 5 (write) 14 (read) 5 (write) 14 (read) 11 (write) 1 (read) Min. Time (access to standalone registers) 1100 4 2 2 5 (write) 11 (read) 5 (write) 11 (read) 6 (write) 1 (read) Units
First activation of SLS after end of reset SLS active after SLS inactive (to start a new communication cycle) SLS active before SCLK active in order to transfer the address byte SLS inactive after SLS active without transfer of data Time after the address transfer to the first data byte transfer Time between two byte transfers (SCLK active to SCLK active) Time to SLS inactive after last byte transfer
TCAN TCAN TCAN TCAN TCAN TCAN TCAN
Note: The RDY signal can be used for a handshake to access to the device. Furthermore, this signal indicates SSC error conditions (see baud rate error detection). Accesses to the device during an SSC error condition can not be correctly taken into account and might lead to errors.
Data Sheet
25
V 1.0D3, 2001-03
82C900
Preliminary Package The 82C900 device is available in a 28-pin P-DSO package. Table 1 contains a functional description of each pin.
Figure 8
P-DSO-28-1 Package
Data Sheet
26
V 1.0D3, 2001-03
82C900
Preliminary
Data Sheet
27
V 1.0D3, 2001-03
((28))
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